Pro IBM unveils new record-breaking chip with 100 billion transistors in less than 1 nanometer footprint — new NanoStack design is like “a 100-storey skyscraper” packed with highly efficient processing power News By Efosa Udinmwen published 29 June 2026 Tiny IBM chip packs more transistors than entire data centres When you purchase through links on our site, we may earn an affiliate commission. Here’s how it works . (Image credit: IBM) Copy link Facebook X Whatsapp Reddit Pinterest Flipboard Threads Email Share this article 0 Join the conversation Follow us Add us as a preferred source on Google Newsletter Subscribe to our newsletter IBM pushes transistor density below the long-feared one-nanometer barrier NanoStack abandons flat chip layouts in favour of vertical transistor stacking The prototype delivered 50% more performance during IBM laboratory testing phases IBM has unveiled what it describes as the world’s first sub-1 nm chip technology, carrying nearly 100 billion transistors on a fingernail-sized surface. The breakthrough revolves around a new 3D NanoStack architecture that moves transistor scaling into the 0.7 nm or 7 angstrom era. For context, today’s most advanced commercial chips typically sit around the 2nm mark, making this a substantial leap in density. Latest Videos From Watch full video here: Building upwards to keep Moore’s Law alive The semiconductor industry has spent decades squeezing more transistors onto increasingly smaller pieces of silicon to improve computing performance. That process has become progressively harder as transistor dimensions approach the scale of only a few atoms across modern processors. You may like Silicon-based qubits have a clear advantage in race to million-qubit quantum computer This device increases computer chip processing speed by 1000 times — without generating extra heat Huawei unveils new chip architecture, which it hopes can help it cut the gap on Nvidia and TSMC IBM’s approach avoids further horizontal compression by stacking transistor layers vertically through a three-dimensional nanosheet architecture instead. The design packs nearly twice the transistor density of IBM’s 2 nm chip technology introduced back in 2021. Are you a pro? Subscribe to our newsletter Sign up to the TechRadar Pro newsletter to get all the top news, opinion, features and guidance your business needs to succeed! Contact me with news and offers from other Future brands Receive email from us on behalf of our trusted partners or sponsors By submitting your information you agree to the Terms & Conditions and Privacy Policy and are aged 16 or over. According to the company, the architecture also delivers approximately 40% greater SRAM scaling to support increasingly demanding AI workloads. This vertical method allows engineers to separate n-type and p-type transistors into distinct layers, which, according to IBM, permits independent optimization of materials for each. , compared it with building a big block of flats rather than houses in a city. What to read next Why IMEC’s new 6G chip breakthrough is exactly what Nvidia’s Jensen Huang is looking for right now Chinese scientists aim to save Moore’s Law by mass-growing 2D materials that ‘outclass silicon’ Key partner to Nvidia, ASML and TSMC brings next-gen RAM and NAND replacements even closer “IBM’s NanoStack is like proposing a 100-storey skyscraper,” said Professor Alan Woodward, a computer scientist at Surrey University. Using this analogy, IBM’s closest competitors, like Intel and Samsung , are somewhere around a 30 to 50-storey building, a far cry from IBM. In testing, the company reported a 50% performance improvement and 70% greater energy efficiency compared with its existing 2nm chips, alongside a 40% gain in on-chip memory scaling. Despite the quoted performance improvements, the technology remains years from commercial use, with IBM estimating production could begin within five years at the earliest. “With our new NanoStack architecture
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